48 search results - page 1 / 10 » Exploiting Low Entropy to Reduce Wire Delay |
CAL
2004
13 years 4 months ago
2004
Wires shrink less efficiently than transistors. Smaller dimensions increase relative delay and the probability of crosstalk. Solutions to this problem include adding additional lat...
ISPD
2010
ACM
13 years 11 months ago
2010
ACM
As the thermal wall becomes the dominant factor limiting VLSI circuit performance, and the interconnect wires become the primary power consumer, power efficiency of onchip data th...
DCC
2005
IEEE
14 years 4 months ago
2005
IEEE
We analyze the technique for reducing the complexity of entropy coding consisting in the a priori grouping of the source alphabet symbols, and in dividing the coding process in tw...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
To achieve minimum signal propagation delay, the nonuniform wire width routing architecture has been widely used in modern VLSI design. The non-uniform routing architecture exploi...
IWANN
2005
Springer
13 years 10 months ago
2005
Springer
Abstract. In this paper we analyse a serial (ripple carry) and a parallel (Kogge-Stone) adder when operating in subthreshold at 100nm and 70nm. These are targeted for ultra low pow...