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» Exploiting Low Entropy to Reduce Wire Delay
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HPCA
2005
IEEE
13 years 11 months ago
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
Rajeev Balasubramonian, Naveen Muralimanohar, Kart...
GLVLSI
2003
IEEE
171views VLSI» more  GLVLSI 2003»
13 years 10 months ago
Combining wire swapping and spacing for low-power deep-submicron buses
We propose an approach for reducing the energy consumption of address buses that targets both the switching and the crosstalk components of power dissipation. The method is based ...
Enrico Macii, Massimo Poncino, Sabino Salerno
ICCCN
2007
IEEE
13 years 11 months ago
Low-Latency Multichannel Wireless Mesh Networks
—Multimedia requirements of the 1990’s drove wired and optical network architects to reconsider the inefficiencies of packet switching and consider long proven methods such as...
Robert McTasney, Dirk Grunwald, Douglas C. Sicker
VLSID
2007
IEEE
120views VLSI» more  VLSID 2007»
14 years 5 months ago
Interframe Bus Encoding Technique for Low Power Video Compression
This paper proposes a data encoder to reduce switched capacitance on system bus. Our method focuses on transferring raw video data (pixels) between off-chip memory and on-chip mem...
Asral Bahari, Tughrul Arslan, Ahmet T. Erdogan
ISWC
2006
IEEE
13 years 11 months ago
Low Power Wearable Audio Player Using Human Body Communications
This paper presents a prototype wearable audio player system to playback the digital audio signal transmitted through the wearer’s body without any wire. To significantly reduce...
Seong-Jun Song, Seung-Jin Lee, Namjun Cho, Hoi-Jun...