5 search results - page 1 / 1 » Exploiting power-up delay for sequential optimization |
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
Recent work has identified the notion of safe replacement for sequential synchronousdesigns that may not have reset hardware or even explicitly known initial states. Safe replace...
ICCD
1996
IEEE
13 years 9 months ago
1996
IEEE
For circuits where there may be latches with no reset line, we show how to replace some of them with combinational logic. All previous work in sequential optimization by latch rem...
MICRO
2009
IEEE
13 years 11 months ago
2009
IEEE
Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have become the de-facto standard in providing scalable communication backbones for mult...
FPGA
2003
ACM
13 years 10 months ago
2003
ACM
The routing channels of an FPGA consist of wire segments of various types providing the tradeoff between performance and routability. In the routing architectures of recently dev...
VLDB
2007
ACM
14 years 5 months ago
2007
ACM
Low-latency and high-throughput processing are key requirements of data stream management systems (DSMSs). Hence, multi-core processors that provide high aggregate processing capa...