Sciweavers

148 search results - page 1 / 30
» Exploiting regularity for low-power design
Sort
View
VLSID
2010
IEEE
173views VLSI» more  VLSID 2010»
13 years 8 months ago
Voltage-Frequency Planning for Thermal-Aware, Low-Power Design of Regular 3-D NoCs
Network-on-Chip combined with Globally Asynchronous Locally Synchronous paradigm is a promising architecture for easy IP integration and utilization with multiple voltage levels. ...
Mohammad Arjomand, Hamid Sarbazi-Azad
DAC
1999
ACM
14 years 5 months ago
A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design
We propose a method for power optimization that considers glitch reduction by gate sizing based on the statistical estimation of glitch transitions. Our method reduces not only th...
Masanori Hashimoto, Hidetoshi Onodera, Keikichi Ta...
TVLSI
2010
12 years 11 months ago
Low-Power Multimedia System Design by Aggressive Voltage Scaling
Mobile multimedia systems are growing in complexity, scalability and thus correspondingly in their implementation challenges. By design, these systems have built-in error resilienc...
Fadi J. Kurdahi, Ahmed M. Eltawil, Kang Yi, Stanle...
AES
2004
Springer
190views Cryptology» more  AES 2004»
13 years 10 months ago
Small Size, Low Power, Side Channel-Immune AES Coprocessor: Design and Synthesis Results
Abstract. When cryptosystems are being used in real life, hardware and software implementations themselves present a fruitful field for attacks. Side channel attacks exploit infor...
Elena Trichina, Tymur Korkishko, Kyung-Hee Lee