9 search results - page 1 / 2 » Exploring DRAM cache architectures for CMP server platforms |
ICCD
2007
IEEE
14 years 1 months ago
2007
IEEE
As dual-core and quad-core processors arrive in the marketplace, the momentum behind CMP architectures continues to grow strong. As more and more cores/threads are placed on-die, ...
IEEEPACT
2007
IEEE
13 years 11 months ago
2007
IEEE
As multi-core architectures flourish in the marketplace, multi-application workload scenarios (such as server consolidation) are growing rapidly. When running multiple application...
CASES
2006
ACM
13 years 11 months ago
2006
ACM
We propose an architecture that uses NAND flash memory to reduce main memory power in web server platforms. Our architecture uses a two level file buffer cache composed of a re...
ICS
2004
Tsinghua U.
13 years 10 months ago
2004
Tsinghua U.
Cache hierarchies have been traditionally designed for usage by a single application, thread or core. As multi-threaded (MT) and multi-core (CMP) platform architectures emerge and...
IISWC
2006
IEEE
13 years 11 months ago
2006
IEEE
— As CMPs are emerging as the dominant architecture for a wide range of platforms (from embedded systems and game consoles, to PCs, and to servers) the need to manage on-chip res...