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» Exploring Memory Hierarchy with ArchC
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GLVLSI
2009
IEEE
158views VLSI» more  GLVLSI 2009»
13 years 9 months ago
Exploration of memory hierarchy configurations for efficient garbage collection on high-performance embedded systems
Modern embedded devices (e.g., PDAs, mobile phones) are now incorporating Java as a very popular implementation language in their designs. These new embedded systems include multi...
José Manuel Velasco, David Atienza, Katzali...
ISLPED
1997
ACM
95views Hardware» more  ISLPED 1997»
13 years 9 months ago
Formalized methodology for data reuse exploration in hierarchical memory mappings
Efficient use of an optimized memory hierarchy to exploit temporal locality in the memory accesses on array signals can have a very large impact on the power consumption in data ...
Jean-Philippe Diguet, Sven Wuytack, Francky Cattho...
VLSID
2001
IEEE
118views VLSI» more  VLSID 2001»
14 years 5 months ago
Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language
Memory represents a major bottleneck in modern embedded systems. Traditionally, memory organizationsfor programmable systems assumed a fixed cache hierarchy. Withthe wideningproce...
Prabhat Mishra, Peter Grun, Nikil D. Dutt, Alexand...
ISSS
2000
IEEE
111views Hardware» more  ISSS 2000»
13 years 9 months ago
Systematic Data Reuse Exploration Methodology for Irregular Access Patterns
Efficient use of an optimized custom memory hierarchy to exploit temporal locality in the memory accesses on array signals can have a very large impact on the power consumption i...
Tanja Van Achteren, Rudy Lauwereins, Francky Catth...