77 search results - page 2 / 16 » Exploring adjacency in floorplanning |
CODES
2006
IEEE
13 years 11 months ago
2006
IEEE
Multi-million gate System-on-Chip (SoC) designs increasingly rely on Intellectual Property (IP) blocks. However, due to technology scaling the leakage power consumption of the IP ...
DAC
2005
ACM
14 years 6 months ago
2005
ACM
Achieving design closure is one of the biggest headaches for modern VLSI designers. This problem is exacerbated by high-level design automation tools that ignore increasingly impo...
ISLPED
2005
ACM
13 years 10 months ago
2005
ACM
Heat is a main concern for processors in deep sub-micron technologies. The chip temperature is affected by both the power consumption of processor components and the chip layout....
ARC
2009
Springer
13 years 12 months ago
2009
Springer
This paper argues the case for the use of analytical models in FPGA architecture layout exploration. We show that the problem when simplified, is amenable to formal optimization t...
ASPDAC
2007
ACM
13 years 9 months ago
2007
ACM
With technology nodes scaling down, the energy consumed by the on-chip intra-tile interconnects is beginning to have a significant impact on the total chip energy. The Energyoptima...