19 search results - page 1 / 4 » Exploring the Limits of Sub-Word Level Parallelism |
IEEEPACT
2000
IEEE
13 years 9 months ago
2000
IEEE
Multimedia instruction set extensions have become a prominent feature in desktop microprocessor platforms, promising superior performance on a wide range of floating-point and int...
HPCA
1998
IEEE
13 years 9 months ago
1998
IEEE
As we look to the future, and the prospect of a billion transistors on a chip, it seems inevitable that microprocessors will exploit having multiple parallel threads. To achieve t...
SIMVIS
2007
13 years 6 months ago
2007
The amount of data to be represented by visualization systems requires new ideas for data processing and representation. As proposed in this contribution, this might be solved by ...
VLSID
2008
IEEE
14 years 5 months ago
2008
IEEE
Simultaneous Multi-Threading (SMT) processors are becoming popular because they exploit both instruction-level and threadlevel parallelism by issuing instructions from different t...
CLUSTER
2007
IEEE
13 years 9 months ago
2007
IEEE
Abstract-- Multicore microprocessors have been largely motivated by the diminishing returns in performance and the increased power consumption of single-threaded ILP microprocessor...