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» Extending JTAG for Testing Signal Integrity in SoCs
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DAC
2002
ACM
14 years 6 months ago
The next chip challenge: effective methods for viable mixed technology SoCs
The next generation of computer chips will continue the trend for more complexity than their predecessors. Many of them will contain different chip technologies and are termed SoC...
H. Bernhard Pogge
ET
2002
122views more  ET 2002»
13 years 5 months ago
Using At-Speed BIST to Test LVDS Serializer/Deserializer Function
LVDS is the acronym for Low-Voltage-DifferentialSignaling and is described in both the ANSI/TIA/EIA644 and IEEE 1596.3 standards. High performance yet Low Power and EMI have made ...
Magnus Eckersand, Fredrik Franzon, Ken Filliter
CCECE
2006
IEEE
13 years 11 months ago
QOS Driven Network-on-Chip Design for Real Time Systems
Real Time embedded system designers are facing extreme challenges in underlying architectural design selection. It involves the selection of a programmable, concurrent, heterogene...
Ankur Agarwal, Mehmet Mustafa, Abhijit S. Pandya
VTC
2008
IEEE
110views Communications» more  VTC 2008»
13 years 11 months ago
FFT Sign Search with Secondary Code Constraints for GNSS Signal Acquisition
— New GNSS signals are usually characterized by the presence of secondary codes and high data rates that can make the sign of the transmitted signal change each primary code peri...
Daniele Borio
IPMI
2003
Springer
13 years 10 months ago
Ideal-Observer Performance under Signal and Background Uncertainty
We use the performance of the Bayesian ideal observer as a figure of merit for hardware optimization because this observer makes optimal use of signal-detection information. Due t...
Subok Park, Matthew A. Kupinski, Eric Clarkson, Ha...