Sciweavers

621 search results - page 2 / 125
» Extending Platform-Based Design to Network on Chip Systems
Sort
View
DATE
2008
IEEE
170views Hardware» more  DATE 2008»
13 years 12 months ago
ETBR: Extended Truncated Balanced Realization Method for On-Chip Power Grid Network Analysis
In this paper, we present a novel simulation approach for power grid network analysis. The new approach, called ETBR for extended truncated balanced realization, is based on model...
Duo Li, Sheldon X.-D. Tan, Bruce McGaughy
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
13 years 9 months ago
VLSI Design of Multi Standard Turbo Decoder for 3G and Beyond
Turbo decoding architectures have greater error correcting capability than any other known code. Due to their excellent performance turbo codes have been employed in several trans...
Imran Ahmed, Tughrul Arslan
ASPDAC
2009
ACM
108views Hardware» more  ASPDAC 2009»
13 years 12 months ago
Synthesis of networks on chips for 3D systems on chips
Three-dimensional stacking of silicon layers is emerging as a promising solution to handle the design complexity and heterogeneity of Systems on Chips (SoCs). Networks on Chips (N...
Srinivasan Murali, Ciprian Seiculescu, Luca Benini...
FPL
2006
Springer
91views Hardware» more  FPL 2006»
13 years 9 months ago
Reconfigurable Systems Enabled by a Network-on-Chip
A modern SoC design comprises dozens of dedicated IP cores for specialized tasks and processors for generalpurpose tasks. Flexibility is the key feature of processors, since it is...
Leandro Möller, Ismael Grehs, Ney Calazans, F...
MSE
2005
IEEE
137views Hardware» more  MSE 2005»
13 years 11 months ago
Teaching SoC Design in a Project-Oriented Course Based on Robotics
The fast growing complexity and short time-tomarket of embedded systems designs, besides the great increase in capacity of today’s chips, are mobilizing the industry towards to ...
Abner Correa Barros, Pericles Lima, Juliana Xavier...