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EIT
2009
IEEE
14 years 2 days ago
System-level memory modeling for bus-based memory architecture exploration
—System-level design (SLD) provides a solution to the challenge of increasing design complexity and time-to-market pressure in modern embedded system designs. In this paper, we p...
Zhongbo Cao, Ramon Mercado, Diane T. Rover
ICEIS
2003
IEEE
13 years 10 months ago
A Multi-Level Architecture for Distributed Object Bases
Abstract: The work described in this article arises from two needs. First, there is still a need for providing more sophisticated database systems than just relational ones. Second...
Markus Kirchberg, Klaus-Dieter Schewe, Alexei Tret...
DATE
2006
IEEE
119views Hardware» more  DATE 2006»
13 years 11 months ago
Performance evaluation for system-on-chip architectures using trace-based transaction level simulation
The ever increasing complexity and heterogeneity of modern System-on-Chip (SoC) architectures make an early and systematic exploration of alternative solutions mandatory. Efficien...
Thomas Wild, Andreas Herkersdorf, Rainer Ohlendorf
ASPDAC
2010
ACM
151views Hardware» more  ASPDAC 2010»
13 years 2 months ago
Source-level timing annotation for fast and accurate TLM computation model generation
This paper proposes a source-level timing annotation method for generation of accurate transaction level models for software computation modules. While Transaction Level Modeling ...
Kai-Li Lin, Chen Kang Lo, Ren-Song Tsay
SBACPAD
2006
IEEE
102views Hardware» more  SBACPAD 2006»
13 years 11 months ago
Ultra-Fast CPU Performance Prediction: Extending the Monte Carlo Approach
Performance evaluation of contemporary processors is becoming increasingly difficult due to the lack of proper frameworks. Traditionally, cycle-accurate simulators have been exte...
Ram Srinivasan, Jeanine Cook, Olaf M. Lubeck