8 search results - page 1 / 2 » Extraction of Gate Level Models from Transistor Circuits by ... |
ICCAD
1991
IEEE
13 years 9 months ago
1991
IEEE
The program TRANALYZE generates a gate-level representation of an MOS transistor circuit. The resulting model contains only four-valued unit and zero delay logic primitives, suita...
ICCAD
2000
IEEE
13 years 10 months ago
2000
IEEE
A high accuracy system for transistor-level static timing analysis is presented. Accurate static timing verification requires that individual gate and interconnect delays be accu...
DAC
2008
ACM
14 years 6 months ago
2008
ACM
Current source based cell models are becoming a necessity for accurate timing and noise analysis at 65nm and below. Voltage waveform shapes are increasingly more difficult to repr...
DATE
2005
IEEE
13 years 11 months ago
2005
IEEE
In nanometer scaled CMOS devices significant increase in the subthreshold, the gate and the reverse biased junction band-toband-tunneling (BTBT) leakage, results in the large incr...
ASPDAC
2004
ACM
13 years 11 months ago
2004
ACM
— Reducing the ever-growing leakage power is critical to power efficient designs. Leakage reduction techniques such as power-gating using sleep transistor insertion introduces la...