276 search results - page 1 / 56 » Extremely Low-Power Logic |
DATE
2004
IEEE
13 years 9 months ago
2004
IEEE
For extremely Low-power Logic, three very new and promising techniques will be described. The first are methods on circuit and system level for reduced supply voltages. In large l...
DAC
2007
ACM
14 years 6 months ago
2007
ACM
This paper presents a variation resilient circuit design technique for maintaining parametric yield of design under inherent variation in process parameters. We propose to utilize...
ISLPED
1998
ACM
13 years 9 months ago
1998
ACM
Adiabatic logic promises extremely low power consumption for those applications where slower clock rates are acceptable. However, there have been very few adiabatic memory designs...
PIMRC
2008
IEEE
13 years 11 months ago
2008
IEEE
Sensor network applications are generally characterized by long idle durations and intermittent communication patterns. The traffic loads are typically so low that overall idle d...
PATMOS
2004
Springer
13 years 10 months ago
2004
Springer
A full-adder implemented by combining branch-based logic and pass-gate logic is presented in this contribution. A comparison between this proposed full-adder (named BBL PT) and its...