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» FADIC: Architectural Synthesis applied in IC Design
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DAC
1995
ACM
13 years 8 months ago
Hierarchical Optimization of Asynchronous Circuits
Abstract— Many asynchronous designs are naturally specified and implemented hierarchically as an interconnection of separate asynchronous modules that operate concurrently and c...
Bill Lin, Gjalt G. de Jong, Tilman Kolks
EDOC
2008
IEEE
13 years 6 months ago
A Model Driven Approach to Represent Sequence Diagrams as Free Choice Petri Nets
Model Driven Development (MDD) aims to promote the role of modeling in Software Engineering. Enterprise systems and architectures are often modeled via multiple representations. F...
Mohamed Ariff Ameedeen, Behzad Bordbar
DAC
2010
ACM
13 years 8 months ago
LUT-based FPGA technology mapping for reliability
As device size shrinks to the nanometer range, FPGAs are increasingly prone to manufacturing defects. We anticipate that the ability to tolerate multiple defects will be very impo...
Jason Cong, Kirill Minkovich
ICCAD
2005
IEEE
147views Hardware» more  ICCAD 2005»
14 years 1 months ago
NoCEE: energy macro-model extraction methodology for network on chip routers
In this paper we present NoCEE, a fast and accurate method for extracting energy models for packet-switched Network on Chip (NoC) routers. Linear regression is used to model the r...
Jeremy Chan, Sri Parameswaran
DAC
2003
ACM
14 years 5 months ago
A scalable software-based self-test methodology for programmable processors
Software-based self-test (SBST) is an emerging approach to address the challenges of high-quality, at-speed test for complex programmable processors and systems-on chips (SoCs) th...
Li Chen, Srivaths Ravi, Anand Raghunathan, Sujit D...