27 search results - page 1 / 6 » FDRA: A Software-Pipelining Algorithm for Embedded VLIW Proc... |
ISSS
2000
IEEE
13 years 8 months ago
2000
IEEE
The paper presents a novel software-pipelining algorithm suitable for optimizing compilers targeting embedded VLIW processors. The proposed algorithm is different from previous ap...
ICCAD
2001
IEEE
14 years 1 months ago
2001
IEEE
In this paper we describe a software pipelining framework, CALiBeR (Cluster Aware Load Balancing Retiming Algorithm), suitable for compilers targeting clustered embedded VLIW proc...
CODES
2001
IEEE
13 years 8 months ago
2001
IEEE
The paper proposes a novel software-pipelining algorithm, Register Sensitive Force Directed Retiming Algorithm (RSFDRA), suitable for optimizing compilers targeting embedded VLIW ...
EMSOFT
2004
Springer
13 years 10 months ago
2004
Springer
Basic retiming is an algorithm originally developed for hardware optimization. Software pipelining is a technique proposed to increase instruction-level parallelism for parallel p...
LCTRTS
2005
Springer
13 years 10 months ago
2005
Springer
Software pipelining is a critical optimization for producing efficient code for VLIW/EPIC and superscalar processors in highperformance embedded applications such as digital sign...