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» FPGA Floating Point Datapath Compiler
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FCCM
2009
IEEE
192views VLSI» more  FCCM 2009»
13 years 11 months ago
FPGA Floating Point Datapath Compiler
This paper will describe the architecture of a compiler which will convert an untimed C description of a set of floating point expressions into a synthesizable datapath optimized ...
Martin Langhammer, Tom VanCourt
FPL
2007
Springer
127views Hardware» more  FPL 2007»
13 years 10 months ago
Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications
This paper presents a novel architecture for domain-specific FPGA devices. This architecture can be optimised for both speed and density by exploiting domain-specific informatio...
Chun Hok Ho, Chi Wai Yu, Philip Heng Wai Leong, Wa...
ARC
2010
Springer
188views Hardware» more  ARC 2010»
13 years 11 months ago
A Fused Hybrid Floating-Point and Fixed-Point Dot-Product for FPGAs
Dot-products are one of the essential and recurrent building blocks in scientific computing, and often take-up a large proportion of the scientific acceleration circuitry. The ac...
Antonio Roldao Lopes, George A. Constantinides
FCCM
2003
IEEE
133views VLSI» more  FCCM 2003»
13 years 10 months ago
Floating Point Unit Generation and Evaluation for FPGAs
Most commercial and academic floating point libraries for FPGAs provide only a small fraction of all possible floating point units. In contrast, the floating point unit generat...
Jian Liang, Russell Tessier, Oskar Mencer
FPGA
2010
ACM
232views FPGA» more  FPGA 2010»
13 years 4 months ago
High-throughput bayesian computing machine with reconfigurable hardware
We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic gr...
Mingjie Lin, Ilia Lebedev, John Wawrzynek