8 search results - page 1 / 2 » FPGA PLB Evaluation using Quantified Boolean Satisfiability |
FPL
2005
Springer
13 years 10 months ago
2005
Springer
This paper describes a novel Field Programmable Gate Array (FPGA) logic synthesis technique which determines if a logic function can be implemented in a given programmable circuit...
FPGA
1998
ACM
13 years 9 months ago
1998
ACM
In this paper, we developed Boolean matching techniques for complex programmable logic blocks (PLBs) in LUT-based FPGAs. A complex PLB can not only be used as a K-input LUT, but a...
ICCAD
2002
IEEE
14 years 1 months ago
2002
IEEE
Within the verification community, there has been a recent increase in interest in Quantified Boolean Formula evaluation (QBF) as many interesting sequential circuit verification ...
JAIR
2006
13 years 4 months ago
2006
Resolution is the rule of inference at the basis of most procedures for automated reasoning. In these procedures, the input formula is first translated into an equisatisfiable for...
DAC
2005
ACM
14 years 5 months ago
2005
ACM
This paper attempts to quantify the optimality of FPGA technology mapping algorithms. We develop an algorithm, based on Boolean satisfiability (SAT), that is able to map a small s...