5 search results - page 1 / 1 » FPGA Routing Architecture: Segmentation and Buffering to Opt... |
FPGA
1999
ACM
13 years 9 months ago
1999
ACM
In this work we investigate the routing architecture of FPGAs, focusing primarily on determining the best distribution of routing segment lengths and the best mix of pass transist...
FPGA
1997
ACM
13 years 9 months ago
1997
ACM
This paper describes an application in high-performance signal processing using reconfigurable computing engines: a 250 MHz cross-correlator for radio astronomy. Experimental resu...
FPGA
2001
ACM
13 years 9 months ago
2001
ACM
The routing architecture of an FPGA consists of the length of the wires, the type of switch used to connect wires (buffered, unbuffered, fast or slow) and the topology of the inte...
DAC
2000
ACM
14 years 6 months ago
2000
ACM
FPGA routing resources typically consist of segments of various lengths. Due to the segmented routing architectures, the traditional measure of wiring cost (wirelength, delay, con...
FPGA
2000
ACM
13 years 9 months ago
2000
ACM
In this paper we revisit the FPGA architectural issue of the effect of logic block functionality on FPGA performance and density. In particular, in the context of lookup table, cl...