44 search results - page 2 / 9 » FPGA Technology Mapping for Power Minimization |
DAC
1993
ACM
13 years 10 months ago
1993
ACM
In this paper we study the area and depth trade-off in LUT based FPGA technology mapping. Starting from a depth-optimal mapping solution, we perform a number of depth relaxation o...
FPGA
2006
ACM
13 years 9 months ago
2006
ACM
Embedded memory blocks are important resources in contemporary FPGA devices. When targeting FPGAs, application designers often specify high-level memory functions which exhibit a ...
TCAD
2010
13 years 16 days ago
2010
Abstract--This paper presents a technology mapping algorithm for field-programmable gate array architectures with dual supply voltages (Vdds) for power optimization. This is done w...
ICCAD
1994
IEEE
13 years 10 months ago
1994
IEEE
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...
FPGA
2010
ACM
14 years 2 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...