14 search results - page 1 / 3 » FPGA architecture for fast parallel computation of co-occurr... |
MAM
2007
13 years 5 months ago
2007
FCCM
2006
IEEE
13 years 11 months ago
2006
IEEE
This paper presents a hardware-optimized variant of the well-known Gaussian elimination over GF(2) and its highly efficient implementation. The proposed hardware architecture, we...
FPL
2010
Springer
13 years 3 months ago
2010
Springer
Significant advances in the field of configurable computing have enabled parallel processing within a single FieldProgrammable Gate Array (FPGA) chip. This paper presents the imple...
IPPS
2006
IEEE
13 years 11 months ago
2006
IEEE
Multi-context FPGAs have multiple memory bits per configuration bit forming configuration planes for fast switching between contexts. Large amount of memory causes significant ove...
ARC
2012
Springer
12 years 1 months ago
2012
Springer
Iterative numerical algorithms with high memory bandwidth requirements but medium-size data sets (matrix size ∼ a few 100s) are highly appropriate for FPGA acceleration. This pap...