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ERSA
2004
129views Hardware» more  ERSA 2004»
13 years 6 months ago
A Methodology for Energy Efficient Application Synthesis Using Platform FPGAs
Platform FPGAs incorporate many different components, such as processor core(s), reconfigurable logic, memory, etc., onto a single chip. When an application is synthesized on platf...
Jingzhao Ou, Viktor K. Prasanna
FCCM
1998
IEEE
169views VLSI» more  FCCM 1998»
13 years 9 months ago
Scalable Network Based FPGA Accelerators for an Automatic Target Recognition Application
Abstract Image processing, specifically Automatic Target Recognition (ATR) in Synthetic Aperture Radar (SAR) imagery, is an application area that can require tremendous processing ...
Ruth Sivilotti, Young Cho, Wen-King Su, Danny Cohe...
FPGA
2000
ACM
128views FPGA» more  FPGA 2000»
13 years 9 months ago
Factoring large numbers with programmable hardware
The fastest known algorithms for factoring large numbers share a core sieving technique. The sieving cores find numbers that are completely factored over a prime base set raised t...
Hea Joung Kim, William H. Mangione-Smith
ERSA
2006
161views Hardware» more  ERSA 2006»
13 years 6 months ago
A Parametric Study of Scalable Interconnects on FPGAs
Abstract-- With the constantly increasing gate capacity of FPGAs, a single FPGA chip is able to employ large-scale applications. To connect a large number of computational nodes, N...
Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Mic...
PPOPP
2012
ACM
12 years 1 months ago
Better speedups using simpler parallel programming for graph connectivity and biconnectivity
Speedups demonstrated for finding the biconnected components of a graph: 9x to 33x on the Explicit Multi-Threading (XMT) many-core computing platform relative to the best serial ...
James A. Edwards, Uzi Vishkin