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    » FPGA power reduction using configurable dual-Vdd
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    TODAES
    2008
    69views more  TODAES 2008»
    Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming
    13 years 5 months ago
    Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming
    Download  www.ee.ucla.edu
    Yu Hu, Yan Lin, Lei He, Tim Tuan
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    DAC
    2008
    ACM
    116views Computer Architecture» more  DAC 2008»
    TuneFPGA: post-silicon tuning of dual-Vdd FPGAs
    14 years 6 months ago
    TuneFPGA: post-silicon tuning of dual-Vdd FPGAs
    Download  users.ece.utexas.edu
    Modern CMOS manufacturing processes have significant variability, which necessitates guard banding to achieve reasonable yield. We study an FPGA architecture with a dual voltage s...
    Stephen Bijansky, Adnan Aziz
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    TCAD
    2010
    97views more  TCAD 2010»
    Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages
    13 years 6 days ago
    Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages
    Download  cadlab.cs.ucla.edu
    Abstract--This paper presents a technology mapping algorithm for field-programmable gate array architectures with dual supply voltages (Vdds) for power optimization. This is done w...
    Deming Chen, Jason Cong, Chen Dong, Lei He, Fei Li...
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    FPGA
    2005
    ACM
    122views FPGA» more  FPGA 2005»
    Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability
    13 years 11 months ago
    Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability
    Download  eda.ee.ucla.edu
    Vdd-programmable FPGAs have been proposed recently to reduce FPGA power, where Vdd levels can be customized for different circuit elements and unused circuit elements can be powe...
    Yan Lin, Fei Li, Lei He
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    ERSA
    2009
    129views Hardware» more  ERSA 2009»
    Data path Configuration Time Reduction for Run-time Reconfigurable Systems
    13 years 3 months ago
    Data path Configuration Time Reduction for Run-time Reconfigurable Systems
    Download  ce.et.tudelft.nl
    - The FPGA (re)configuration is a time-consuming process and a bottleneck in FPGA-based Run-Time Reconfigurable (RTR) systems. In this paper, we present a High Level Synthesis (HLS...
    Mahmood Fazlali, Ali Zakerolhosseini, Mojtaba Sabe...
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