87 search results - page 2 / 18 » FPGA technology mapping: a study of optimality |
FPGA
2006
ACM
13 years 9 months ago
2006
ACM
Abstract--Field-programmable gate-array (FPGA) logic synthesis and technology mapping have been studied extensively over the past 15 years. However, progress within the last few ye...
FPGA
1995
ACM
13 years 9 months ago
1995
ACM
We study the nominal delay minimization problem in LUTbased FPGA technologymapping, where interconnect delay is assumed proportionalto net fanout size. We prove that the delay-opt...
ICCAD
2004
IEEE
14 years 2 months ago
2004
IEEE
In this paper we study the technology mapping problem for FPGA architectures to minimize chip area, or the total number of lookup tables (LUTs) of the mapped design, under the chi...
DAC
1996
ACM
13 years 9 months ago
1996
ACM
FPGA
2008
ACM
13 years 6 months ago
2008
ACM
This paper presents a new technology mapper, WireMap. The mapper uses an edge flow heuristic to improve the routability of a mapped design. The heuristic is applied during the ite...