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ICCAD
2010
IEEE
140views Hardware» more  ICCAD 2010»
13 years 3 months ago
Polynomial datapath optimization using constraint solving and formal modelling
For a variety of signal processing applications polynomials are implemented in circuits. Recent work on polynomial datapath optimization achieved significant reductions of hardware...
Finn Haedicke, Bijan Alizadeh, Görschwin Fey,...
DATE
2009
IEEE
120views Hardware» more  DATE 2009»
14 years 10 days ago
Optimizing data flow graphs to minimize hardware implementation
Abstract - This paper describes an efficient graphbased method to optimize data-flow expressions for best hardware implementation. The method is based on factorization, common su...
Daniel Gomez-Prado, Q. Ren, Maciej J. Ciesielski, ...
ISCAS
2003
IEEE
100views Hardware» more  ISCAS 2003»
13 years 11 months ago
Area-effective FIR filter design for multiplier-less implementation
The hardware complexity of digital filters is not controllable by straightforwardly rounding the coefficients to the quantization levels. In this paper, we propose an effective al...
Tay-Jyi Lin, Tsung-Hsun Yang, Chein-Wei Jen
JLP
2008
129views more  JLP 2008»
13 years 5 months ago
Program and proof optimizations with type systems
We demonstrate a method for describing data-flow analyses based program optimizations as compositional type systems with a transformation component. Analysis results are presented...
Ando Saabas, Tarmo Uustalu
ECCC
2011
223views ECommerce» more  ECCC 2011»
13 years 17 days ago
A Case of Depth-3 Identity Testing, Sparse Factorization and Duality
Polynomial identity testing (PIT) problem is known to be challenging even for constant depth arithmetic circuits. In this work, we study the complexity of two special but natural ...
Chandan Saha, Ramprasad Saptharishi, Nitin Saxena