4 search results - page 1 / 1 » Failure analysis for ultra low power nano-CMOS SRAM under pr... |
SOCC
2008
IEEE
13 years 11 months ago
2008
IEEE
— Several design metrics have been used in the past to evaluate the SRAM cell stability. However, most of them fail to provide the exact stability figures as shown in this paper...
ISCAS
2008
IEEE
13 years 11 months ago
2008
IEEE
— In a nanoscale technology, memory bits are highly susceptible to process variation induced read/write failures. To address the above problem, in this paper a new memory cell is...
DAC
2006
ACM
14 years 5 months ago
2006
ACM
Increasing source voltage (Source-Biasing) is an efficient technique for reducing gate and sub-threshold leakage of SRAM arrays. However, due to process variation, a higher source...
ISVLSI
2002
IEEE
13 years 9 months ago
2002
IEEE
With technology scaling, power supply and threshold voltage continue to decrease to satisfy high performance and low power requirements. In the past, subthreshold CMOS circuits ha...