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» Fame as an Effect of the Memory Size
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HPCA
2005
IEEE
14 years 5 months ago
Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions
The use of large instruction windows coupled with aggressive out-oforder and prefetching capabilities has provided significant improvements in processor performance. In this paper...
Aamer Jaleel, Bruce L. Jacob
DAC
2009
ACM
14 years 6 months ago
Improving STT MRAM storage density through smaller-than-worst-case transistor sizing
This paper presents a technique to improve the storage density of spin-torque transfer (STT) magnetoresistive random access memory (MRAM) in the presence of significant magnetic t...
Wei Xu, Yiran Chen, Xiaobin Wang, Tong Zhang
IPPS
2005
IEEE
13 years 11 months ago
A Cost-Effective Main Memory Organization for Future Servers
Today, the amount of main memory in mid-range servers is pushing practical limits with as much as 192 GB memory in a 24 processor system [21]. Further, with the onset of multi-thr...
Magnus Ekman, Per Stenström
WMPI
2004
ACM
13 years 11 months ago
Understanding the effects of wrong-path memory references on processor performance
High-performance out-of-order processors spend a significant portion of their execution time on the incorrect program path even though they employ aggressive branch prediction al...
Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale ...
IEEEPACT
2002
IEEE
13 years 10 months ago
Cost Effective Memory Dependence Prediction using Speculation Levels and Color Sets
Memory dependence prediction allows out-of-order issue processors to achieve high degrees of instruction level parallelism by issuing load instructions at the earliest time withou...
Soner Önder