Sciweavers

28 search results - page 1 / 6
» Fast Buffered Delay Estimation Considering Process Variation...
Sort
View
ASPDAC
2007
ACM
86views Hardware» more  ASPDAC 2007»
13 years 9 months ago
Fast Buffered Delay Estimation Considering Process Variations
- Advanced process technologies impose more significant challenges especially when manufactured circuits exhibit substantial process variations. Consideration of process variations...
Tien-Ting Fang, Ting-Chi Wang
ISPD
2006
ACM
90views Hardware» more  ISPD 2006»
13 years 11 months ago
Fast buffer insertion considering process variations
Advanced process technologies call for a proactive consideration of process variations in design to ensure high parametric timing yield. Despite of its popular use in almost any h...
Jinjun Xiong, Lei He
DAC
2007
ACM
14 years 6 months ago
Fast Min-Cost Buffer Insertion under Process Variations
Process variation has become a critical problem in modern VLSI fabrication. In the presence of process variation, buffer insertion problem under performance constraints becomes mo...
Ruiming Chen, Hai Zhou
ICCD
2005
IEEE
90views Hardware» more  ICCD 2005»
13 years 10 months ago
Variability-Driven Buffer Insertion Considering Correlations
— In this work we investigate the buffer insertion problem under process variations. Sub 100-nm fabrication process causes significant variations on many design parameters. We p...
Azadeh Davoodi, Ankur Srivastava
DAC
2004
ACM
14 years 6 months ago
Statistical optimization of leakage power considering process variations using dual-Vth and sizing
timing analysis tools to replace standard deterministic static timing analyzers whereas [8,27] develop approaches for the statistical estimation of leakage power considering within...
Ashish Srivastava, Dennis Sylvester, David Blaauw