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» Fast Comparisons of Circuit Implementations
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DATE
2004
IEEE
125views Hardware» more  DATE 2004»
13 years 8 months ago
Fast Comparisons of Circuit Implementations
Abstract-- Digital designs can be mapped to different implementations using diverse approaches, with varying cost criteria. Post-processing transforms, such as transistor sizing ca...
Shrirang K. Karandikar, Sachin S. Sapatnekar
ICCD
2008
IEEE
160views Hardware» more  ICCD 2008»
14 years 1 months ago
Fast arbiters for on-chip network switches
— The need for efficient implementation of simple crossbar schedulers has increased in the recent years due to the advent of on-chip interconnection networks that require low la...
Giorgos Dimitrakopoulos, Nikos Chrysos, Costas Gal...
ARVLSI
2001
IEEE
289views VLSI» more  ARVLSI 2001»
13 years 8 months ago
A High-Performance 64-bit Adder Implemented in Output Prediction Logic
Output Prediction Logic (OPL) is a technique that can be applied to conventional CMOS logic families to obtain considerable speedups. When applied to static CMOS, OPL retains the ...
Sheng Sun, Larry McMurchie, Carl Sechen
CORR
2008
Springer
118views Education» more  CORR 2008»
13 years 4 months ago
A Logic Programming Framework for Combinational Circuit Synthesis
Abstract. Logic Programming languages and combinational circuit synthesis tools share a common "combinatorial search over logic formulae" background. This paper attempts ...
Paul Tarau, Brenda Luderman
FPL
2005
Springer
79views Hardware» more  FPL 2005»
13 years 10 months ago
FPGA-based implementation and comparison of recursive and iterative algorithms
The paper analyses and compares alternative iterative and recursive implementations of FPGA circuits for various problems. Two types of recursive calls have been examined, namely ...
Valery Sklyarov, Iouliia Skliarova, Bruno Figueire...