19 search results - page 1 / 4 » Fast Instruction Cache Simulation Strategies in a Hardware S... |
ASPDAC
1999
ACM
13 years 9 months ago
1999
ACM
PARA
2004
Springer
13 years 10 months ago
2004
Springer
Cache optimizations typically include code transformations to increase the locality of memory accesses. An orthogonal approach is to enable for latency hiding by introducing prefet...
CODES
2009
IEEE
13 years 11 months ago
2009
IEEE
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
MICRO
1995
IEEE
13 years 8 months ago
1995
IEEE
Software prefetching, typically in the context of numericor loop-intensive benchmarks, has been proposed as one remedy for the performance bottleneck imposed on computer systems b...
ASPLOS
2004
ACM
13 years 10 months ago
2004
ACM
Tracing garbage collectors traverse references from live program variables, transitively tracing out the closure of live objects. Memory accesses incurred during tracing are essen...