19 search results - page 2 / 4 » Fast Instruction Cache Simulation Strategies in a Hardware S... |
CODES
1998
IEEE
13 years 9 months ago
1998
IEEE
Timing analysis for checking satisfaction of constraints is a crucial problem in real-time system design. In some current approaches, the delay of software modules is precalculate...
ISPASS
2009
IEEE
14 years 4 days ago
2009
IEEE
Trace-driven simulation of superscalar processors is particularly complicated. The dynamic nature of superscalar processors combined with the static nature of traces can lead to l...
ISSS
2002
IEEE
13 years 10 months ago
2002
IEEE
Adding a small loop cache to a microprocessor has been shown to reduce average instruction fetch energy for various sets of embedded system applications. With the advent of core-b...
DAC
2008
ACM
14 years 6 months ago
2008
ACM
With the growing number of programmable processing elements in today's MultiProcessor System-on-Chip (MPSoC) designs, the synergy required for the development of the hardware...
CODES
2008
IEEE
13 years 11 months ago
2008
IEEE
Application-specific system-on-chip platforms create the opportunity to customize the cache configuration for optimal performance with minimal chip estate. Simulation, in partic...