8 search results - page 2 / 2 » Fast timing analysis of plane circuits via two-layer CNN-bas... |
DAC
2000
ACM
13 years 9 months ago
2000
ACM
The decrease in feature size and added chip functionality in large sub-micron integrated circuits demand larger grids for power distribution. Since power grids are performance lim...
SAC
2006
ACM
13 years 11 months ago
2006
ACM
: In chip design, one of the main objectives is to decrease its clock cycle; however, the existing approaches to timing analysis under uncertainty are based on fundamentally restri...
DAC
2006
ACM
14 years 6 months ago
2006
ACM
Existing approaches to timing analysis under uncertainty are based on restrictive assumptions. Statistical STA techniques assume that the full probabilistic distribution of parame...