26 search results - page 1 / 6 » Faster projection based methods for circuit level verificati... |
ASPDAC
2008
ACM
13 years 6 months ago
2008
ACM
As VLSI fabrication technology progresses to 65nm feature sizes and smaller, transistors no longer operate as ideal switches. This motivates the verification of digital circuits us...
FMCAD
2007
Springer
13 years 8 months ago
2007
Springer
As VLSI fabrication technology progresses to 65nm feature sizes and smaller, transistors no longer operate as ideal switches. This motivates verifying digital circuits using contin...
VLSI
2007
Springer
13 years 10 months ago
2007
Springer
— Software simulation remains the most used method for VHDL RTL functional verification. The functional verification process essentially consists of two parts. The first one is t...
ISQED
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper describes the use of integer equations for high level modeling digital circuits for application of formal verification properties at this level. Most formal verificatio...
DATE
1999
IEEE
13 years 9 months ago
1999
IEEE
If real number calculations are implemented as circuits, only a limited preciseness can be obtained. Hence, formal verification can not be used to prove the equivalence between th...