327 search results - page 3 / 66 » Fault emulation: a new approach to fault grading |
FPL
2004
Springer
13 years 11 months ago
2004
Springer
This paper presents a novel approach to interconnect fault location for FPGAs during power-on sequence. The method is based on a concept known as fault grading which utilizes defec...
FPGA
2003
ACM
13 years 11 months ago
2003
ACM
This paper proposes a new high-level technique for designing fault tolerant systems in SRAM-based FPGAs, without modifications in the FPGA architecture. Traditionally, TMR has bee...
IOLTS
2006
IEEE
13 years 11 months ago
2006
IEEE
FPGA emulation has proven to be a performance effective method to analyse the behaviour of digital circuits in the presence of soft errors due to SEU effects. In particular, the r...
FPL
2001
Springer
13 years 10 months ago
2001
Springer
Designers of safety-critical VLSI systems are asking for effective tools for evaluating and validating their designs. Fault Injection is commonly adopted for this task, and its eff...
ET
2007
13 years 5 months ago
2007
This article describes an emulation-based method for locating stuck-at faults in combinational and synchronous sequential circuits. The method is based on automatically designing a...