4 search results - page 1 / 1 » Fault models for embedded-DRAM macros |
DAC
2009
ACM
14 years 5 months ago
2009
ACM
In this paper, we compare embedded-DRAM (eDRAM) testing to both SRAM testing and commodity-DRAM testing, since an eDRAM macro uses DRAM cells with an SRAM interface. We first star...
DFT
1999
IEEE
13 years 9 months ago
1999
IEEE
A programmable single-chip multiprocessor system for video coding has been developed. The system is implemented in a high-performance 0.25 m logic/embedded DRAM process. It integr...
ICCAD
1994
IEEE
13 years 8 months ago
1994
IEEE
We consider the problem of testing for delay faults in macrobased circuits. Macro-based circuits are obtained as a result of technology mapping. Gate-level fault models cannot be ...
ISQED
2002
IEEE
13 years 9 months ago
2002
IEEE
The paper addresses the issue of microprocessor and microcontroller testing, and follows an approach based on the generation of a test program. The proposed method relies on two p...