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» Fault tolerant clockless wave pipeline design
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SIROCCO
2007
13 years 7 months ago
Design of Minimal Fault Tolerant On-Board Networks: Practical Constructions
Abstract. The problem we consider originates from the design of efficient on-board networks in satellites (also called Traveling Wave Tube Amplifiers). Signals incoming in the net...
Jean-Claude Bermond, Frédéric Giroir...
MICRO
2010
IEEE
167views Hardware» more  MICRO 2010»
13 years 3 months ago
Erasing Core Boundaries for Robust and Configurable Performance
Single-thread performance, reliability and power efficiency are critical design challenges of future multicore systems. Although point solutions have been proposed to address thes...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Scott ...
SBCCI
2005
ACM
123views VLSI» more  SBCCI 2005»
13 years 11 months ago
Fault tolerance overhead in network-on-chip flow control schemes
Flow control mechanisms in Network-on-Chip (NoC) architectures are critical for fast packet propagation across the network and for low idling of network resources. Buffer manageme...
Antonio Pullini, Federico Angiolini, Davide Bertoz...
DATE
2010
IEEE
161views Hardware» more  DATE 2010»
13 years 11 months ago
Aging-resilient design of pipelined architectures using novel detection and correction circuits
—Time-dependent performance degradation due to transistor aging caused by mechanisms such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) is one o...
Hamed F. Dadgour, Kaustav Banerjee
ICPPW
2009
IEEE
13 years 3 months ago
Analyzing Checkpointing Trends for Applications on the IBM Blue Gene/P System
Current petascale systems have tens of thousands of hardware components and complex system software stacks, which increase the probability of faults occurring during the lifetime ...
Harish Gapanati Naik, Rinku Gupta, Pete Beckman