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ET
2002
64views more  ET 2002»
13 years 5 months ago
Structural Fault Based Specification Reduction for Testing Analog Circuits
Specification reduction can reduce test time, consequently, test cost. In this paper, a methodology to reduce specifications during specification testing for analog circuit is prop...
Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen
EAAI
2010
130views more  EAAI 2010»
13 years 6 months ago
Fault diagnosis in railway track circuits using Dempster-Shafer classifier fusion
This paper addresses the problem of fault detection and isolation in railway track circuits. A track circuit can be considered as a large-scale system composed of a series of trim...
Latifa Oukhellou, Alexandra Debiolles, Thierry Den...
DATE
2002
IEEE
98views Hardware» more  DATE 2002»
13 years 11 months ago
A Test Design Method for Floating Gate Defects (FGD) in Analog Integrated Circuits
A unified approach to fault simulation for FGDs is introduced. Instead of a direct fault simulation, the proposed approach calculates indirectly from the simulator output the set...
Michael Pronath, Helmut E. Graeb, Kurt Antreich
ICCAD
2000
IEEE
171views Hardware» more  ICCAD 2000»
13 years 10 months ago
A Parametric Test Method for Analog Components in Integrated Mixed-Signal Circuits
In this paper, we present a novel approach to use test stimuli generated by digital components of a mixed-signal circuit for testing its analog components. A wavelet transform is ...
Michael Pronath, Volker Gloeckel, Helmut E. Graeb
DSD
2007
IEEE
98views Hardware» more  DSD 2007»
14 years 11 days ago
Fault Diagnosis in Integrated Circuits with BIST
This paper presents an optimized fault diagnosing procedure applicable in Built-in Self-Test environments. Instead of the known approach based on a simple bisection of patterns in...
Raimund Ubar, Sergei Kostin, Jaan Raik, Teet Evart...