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IJPP
2007
56views more  IJPP 2007»
13 years 4 months ago
Fault-aware Communication Mapping for NoCs with Guaranteed Latency
As feature sizes shrink, transient failures of on-chip network links become a critical problem. At the same time, many applications require guarantees on both message arrival prob...
Sorin Manolache, Petru Eles, Zebo Peng
CODES
2005
IEEE
13 years 10 months ago
Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs
To ensure low power consumption while maintaining flexibility and performance, future Systems-on-Chip (SoC) will combine several types of processor cores and data memory units of...
Anthony Leroy, Paul Marchal, Adelina Shickova, Fra...
RSP
2005
IEEE
131views Control Systems» more  RSP 2005»
13 years 10 months ago
Models for Embedded Application Mapping onto NoCs: Timing Analysis
Networks-on-chip (NoCs) are an emergent communication infrastructure, which can be designed to deal with growing system complexity and technology evolution. The efficient use of N...
César A. M. Marcon, Márcio Eduardo K...
CODES
2007
IEEE
13 years 6 months ago
Incremental run-time application mapping for homogeneous NoCs with multiple voltage levels
In this paper, we propose an efficient technique for run-time application mapping onto Network-on-Chip (NoC) platforms with multiple voltage levels. Our technique consists of a re...
Chen-Ling Chou, Radu Marculescu
VLSID
2010
IEEE
173views VLSI» more  VLSID 2010»
13 years 8 months ago
Voltage-Frequency Planning for Thermal-Aware, Low-Power Design of Regular 3-D NoCs
Network-on-Chip combined with Globally Asynchronous Locally Synchronous paradigm is a promising architecture for easy IP integration and utilization with multiple voltage levels. ...
Mohammad Arjomand, Hamid Sarbazi-Azad