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DSD
2010
IEEE
111views Hardware» more  DSD 2010»
11 years 3 days ago
Faults Coverage Improvement Based on Fault Simulation and Partial Duplication
— A method how to improve the coverage of single faults in combinational circuits is proposed. The method is based on Concurrent Error Detection, but uses a fault simulation to f...
Jaroslav Borecky, Martin Kohlik, Hana Kubatova, Pa...
DSN
2008
IEEE
11 years 8 months ago
Using likely program invariants to detect hardware errors
In the near future, hardware is expected to become increasingly vulnerable to faults due to continuously decreasing feature size. Software-level symptoms have previously been used...
Swarup Kumar Sahoo, Man-Lap Li, Pradeep Ramachandr...
ETS
2009
IEEE
79views Hardware» more  ETS 2009»
10 years 11 months ago
Concurrent Self-Test with Partially Specified Patterns for Low Test Latency and Overhead
Structural on-line self-test may be performed to detect permanent faults and avoid their accumulation. This paper improves concurrent BIST techniques based on a deterministic test ...
Michael A. Kochte, Christian G. Zoellin, Hans-Joac...
ICCAD
1995
IEEE
170views Hardware» more  ICCAD 1995»
11 years 5 months ago
Acceleration techniques for dynamic vector compaction
: We present several techniques for accelerating dynamic vector compaction for combinational and sequential circuits. A key feature of all our techniques is that they significantly...
Anand Raghunathan, Srimat T. Chakradhar
ITC
2003
IEEE
127views Hardware» more  ITC 2003»
11 years 6 months ago
Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects
In this paper, we study the possibility of using logic defect-level prediction models to predict the detection behavior of statistical timing defects. We compare two known logic m...
Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting...
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