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DAC
2008
ACM
14 years 5 months ago
An 8x8 run-time reconfigurable FPGA embedded in a SoC
This paper presents a RTR FPGA embedded in a System on Chip fabricated in 130nm CMOS process. Various aspects of the design flow, from automation to floor-planning are discussed. ...
Sumanta Chaudhuri, Sylvain Guilley, Florent Flamen...
FPL
2006
Springer
147views Hardware» more  FPL 2006»
13 years 8 months ago
Secure Content Distribution System Based on Run-Time Partial Hardware Reconfiguration
A secure content distribution system is prototyped based on run-time partial reconfigurability of an FPGA. The system provides a robust content protection scheme for online conten...
Yohei Hori, Hiroyuki Yokoyama, Kenji Toda
FPGA
2007
ACM
124views FPGA» more  FPGA 2007»
13 years 8 months ago
Efficient hardware checkpointing: concepts, overhead analysis, and implementation
Progress in reconfigurable hardware technology allows the implementation of complete SoCs in today's FPGAs. In the context design for reliability, software checkpointing is a...
Dirk Koch, Christian Haubelt, Jürgen Teich
COMPSEC
2008
116views more  COMPSEC 2008»
13 years 4 months ago
Enforcing memory policy specifications in reconfigurable hardware
While general-purpose processor based systems are built to enforce memory protection to prevent the unintended sharing of data between processes, current systems built around reco...
Ted Huffmire, Timothy Sherwood, Ryan Kastner, Timo...
RSP
2006
IEEE
116views Control Systems» more  RSP 2006»
13 years 10 months ago
Performance Evaluation of an Adaptive FPGA for Network Applications
This paper presents the design and the performance evaluation of a coarse-grain dynamically reconfigurable platform for network applications. The platform consists of two MicroBla...
Christoforos Kachris, Stamatis Vassiliadis