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» Finding heap-bounds for hardware synthesis
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ASPDAC
1995
ACM
127views Hardware» more  ASPDAC 1995»
13 years 8 months ago
Reclocking for high-level synthesis
In this paper we describe, a powerful post-synthesis approach called reclocking, for performance improvement by minimizing the total execution time. By back annotating the wire del...
Pradip K. Jha, Nikil D. Dutt, Sri Parameswaran
CORR
2006
Springer
112views Education» more  CORR 2006»
13 years 5 months ago
High-level synthesis under I/O Timing and Memory constraints
The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper...
Philippe Coussy, Gwenolé Corre, Pierre Bome...
ASYNC
2004
IEEE
98views Hardware» more  ASYNC 2004»
13 years 9 months ago
Synthesis of Speed Independent Circuits Based on Decomposition
This paper presents a decomposition method for speedindependent circuit design that is capable of significantly reducing the cost of synthesis. In particular, this method synthesi...
Tomohiro Yoneda, Hiroomi Onda, Chris J. Myers
ICCAD
1998
IEEE
153views Hardware» more  ICCAD 1998»
13 years 9 months ago
Intellectual property protection by watermarking combinational logic synthesis solutions
The intellectual property (IP) business model is vulnerable to a number of potentially devastating obstructions, such as misappropriation and intellectual property fraud. We propo...
Darko Kirovski, Yean-Yow Hwang, Miodrag Potkonjak,...
TCAD
2002
139views more  TCAD 2002»
13 years 4 months ago
Digital filter synthesis based on an algorithm to generate all minimal signed digit representations
In this paper, the authors propose an algorithm to find all the minimal signed digit (MSD) representations of a constant and present an algorithm to synthesize digital filters base...
In-Cheol Park, Hyeong-Ju Kang