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» Finding heap-bounds for hardware synthesis
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FPGA
2009
ACM
180views FPGA» more  FPGA 2009»
14 years 25 days ago
Scalable don't-care-based logic optimization and resynthesis
We describe an optimization method for combinational and sequential logic networks, with emphasis on scalability and the scope of optimization. The proposed resynthesis (a) is cap...
Alan Mishchenko, Robert K. Brayton, Jie-Hong Rolan...
ACSD
2009
IEEE
106views Hardware» more  ACSD 2009»
13 years 8 months ago
Specification Enforcing Refinement for Convertibility Verification
Protocol conversion deals with the automatic synthesis of an additional component, often referred to as an adaptor or a converter, to bridge mismatches between interacting compone...
Partha S. Roop, Alain Girault, Roopak Sinha, Grego...
CAV
2008
Springer
139views Hardware» more  CAV 2008»
13 years 8 months ago
CSIsat: Interpolation for LA+EUF
We present CSIsat, an interpolating decision procedure for the quantifier-free theory of rational linear arithmetic and equality with uninterpreted function symbols. Our implementa...
Dirk Beyer, Damien Zufferey, Rupak Majumdar
DAC
2007
ACM
14 years 7 months ago
Global Critical Path: A Tool for System-Level Timing Analysis
An effective method for focusing optimization effort on the most important parts of a design is to examine those elements on the critical path. Traditionally, the critical path is...
Girish Venkataramani, Mihai Budiu, Tiberiu Chelcea...
DATE
2010
IEEE
146views Hardware» more  DATE 2010»
13 years 11 months ago
Leveraging application-level requirements in the design of a NoC for a 4G SoC - a case study
—In this paper, we examine the design process of a Network on-Chip (NoC) for a high-end commercial System onChip (SoC) application. We present several design choices and focus on...
Rudy Beraha, Isask'har Walter, Israel Cidon, Avino...