21 search results - page 3 / 5 » Fire-and-Forget: Load Store Scheduling with No Store Queue a... |
ISLPED
2006
ACM
13 years 11 months ago
2006
ACM
Buffering more in-flight instructions in an out-of-order microprocessor is a straightforward and effective method to help tolerate the long latencies generally associated with ...
JILP
2000
13 years 5 months ago
2000
Load latency remains a signi cant bottleneck in dynamically scheduled pipelined processors. Load speculation techniques have been proposed to reduce this latency. Dependence Predi...
MICRO
2005
IEEE
13 years 11 months ago
2005
IEEE
This paper describes a scalable, low-complexity alternative to the conventional load/store queue (LSQ) for superscalar processors that execute load and store instructions speculat...
HPCA
2000
IEEE
13 years 10 months ago
2000
IEEE
We consider a variety of dynamic, hardware-based methods for exploiting load/store parallelism, including mechanisms that use memory dependence speculation. While previous work ha...
TVLSI
2008
13 years 5 months ago
2008
This paper proposes a high-performance scalable quality-of-service (QoS)-aware memory controller for the packet memory where packet data are stored in network routers. A major chal...