Sciweavers

17 search results - page 2 / 4
» Fitted Elmore Delay: A Simple and Accurate Interconnect Dela...
Sort
View
ISPD
1997
ACM
186views Hardware» more  ISPD 1997»
13 years 9 months ago
EWA: exact wiring-sizing algorithm
The wire sizing problem under inequality Elmore delay constraints is known to be posynomial, hence convex under an exponential variable-transformation. There are formal methods fo...
Rony Kay, Gennady Bucheuv, Lawrence T. Pileggi
ISPD
1999
ACM
95views Hardware» more  ISPD 1999»
13 years 9 months ago
Incremental capacitance extraction and its application to iterative timing-driven detailed routing
In this paper, we consider delay optimization in multilayer detailed routing. Given a detailed routing by some detailed router, we iteratively improve the delays of critical nets ...
Yanhong Yuan, Prithviraj Banerjee
ASPDAC
2006
ACM
135views Hardware» more  ASPDAC 2006»
13 years 10 months ago
Robust analytical gate delay modeling for low voltage circuits
— Sakurai-Newton (SN) delay metric [1] is a widely used closed form delay metric for CMOS gates because of simplicity and reasonable accuracy. Nevertheless it can be shown that t...
Anand Ramalingam, Sreekumar V. Kodakara, Anirudh D...
ICCAD
2001
IEEE
152views Hardware» more  ICCAD 2001»
14 years 1 months ago
Hybrid Structured Clock Network Construction
This paper hierarchically constructs a hybrid mesh/tree clock network structure consisting of overlying zero-skew clock meshes, with underlying zero-skew clock trees originating f...
Haihua Su, Sachin S. Sapatnekar
EURODAC
1994
IEEE
127views VHDL» more  EURODAC 1994»
13 years 8 months ago
Optimal equivalent circuits for interconnect delay calculations using moments
In performance-driven interconnect design, delay estimators are used to determine both the topology and the layout of good routing trees. We address the class of moment-matching, ...
Sudhakar Muddu, Andrew B. Kahng