Sciweavers

6 search results - page 1 / 2
» FlexCache: A Framework for Flexible Compiler Generated Data ...
Sort
View
IMS
2000
145views Hardware» more  IMS 2000»
13 years 8 months ago
FlexCache: A Framework for Flexible Compiler Generated Data Caching
Csaba Andras Moritz, Matthew Frank, Saman P. Amara...
MICRO
2003
IEEE
147views Hardware» more  MICRO 2003»
13 years 10 months ago
Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors
Wire delays are a major concern for current and forthcoming processors. One approach to attack this problem is to divide the processor into semi-independent units referred to as c...
Enric Gibert, F. Jesús Sánchez, Anto...
ASPLOS
1998
ACM
13 years 9 months ago
Cache-Conscious Data Placement
As the gap between memory and processor speeds continues to widen, cache efficiency is an increasingly important component of processor performance. Compiler techniques have been...
Brad Calder, Chandra Krintz, Simmi John, Todd M. A...
CODES
2009
IEEE
13 years 11 months ago
Using binary translation in event driven simulation for fast and flexible MPSoC simulation
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
Marius Gligor, Nicolas Fournel, Frédé...
ICS
2007
Tsinghua U.
13 years 11 months ago
Optimization of data prefetch helper threads with path-expression based statistical modeling
This paper investigates helper threads that improve performance by prefetching data on behalf of an application’s main thread. The focus is data prefetch helper threads that lac...
Tor M. Aamodt, Paul Chow