36 search results - page 3 / 8 » Floating Point Unit Generation and Evaluation for FPGAs |
ARITH
2005
IEEE
13 years 10 months ago
2005
IEEE
The floating-point unit in the Synergistic Processor Element of the 1st generation multi-core CELL Processor is described. The FPU supports 4-way SIMD single precision and intege...
CSSE
2008
IEEE
13 years 6 months ago
2008
IEEE
According to dramatically growing interesting in power-efficient embedded processor, designers must establish the proper power strategy when they design new embedded processor core...
FPL
2001
Springer
13 years 9 months ago
2001
Springer
This paper presents parameterized module-generators for pipelined function evaluation using lookup tables, adders, shifters and multipliers. We discuss trade-offs involved between...
ARITH
2009
IEEE
13 years 8 months ago
2009
IEEE
This paper deals with the design and implementation of low latency software for binary floating-point division with correct rounding to nearest. The approach we present here targe...
RSP
2008
IEEE
13 years 11 months ago
2008
IEEE
Current graphic cards include advanced graphic processing units to accelerate the rendering of 3D objects with millions of polygons. As object models grow in complexity, the rende...