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ARITH
1999
IEEE
13 years 9 months ago
Floating-Point Unit in Standard Cell Design with 116 Bit Wide Dataflow
The floating-point unit of a S/390 CMOS microprocessor is described. It contains a 116 bit fraction dataflow for addition and subtraction and a 64 bit-wide multiplier. Besides the...
Guenter Gerwig, Michael Kroener
IPPS
2005
IEEE
13 years 10 months ago
Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores
The use of pipelined floating-point arithmetic cores to create high-performance FPGA-based computational kernels has introduced a new class of problems that do not exist when usi...
Ling Zhuo, Gerald R. Morris, Viktor K. Prasanna
ARITH
1999
IEEE
13 years 9 months ago
Correctness Proofs Outline for Newton-Raphson Based Floating-Point Divide and Square Root Algorithms
This paper describes a study of a class of algorithms for the floating-point divide and square root operations, based on the Newton-Raphson iterative method. The two main goals we...
Marius A. Cornea-Hasegan, Roger A. Golliver, Peter...
GLVLSI
1998
IEEE
119views VLSI» more  GLVLSI 1998»
13 years 9 months ago
A Combined Interval and Floating Point Multiplier
Interval arithmetic provides an e cient method for monitoring and controlling errors in numerical calculations. However, existing software packages for interval arithmetic are oft...
James E. Stine, Michael J. Schulte
ARC
2008
Springer
115views Hardware» more  ARC 2008»
13 years 7 months ago
A High Throughput FPGA-based Floating Point Conjugate Gradient Implementation
As Field Programmable Gate Arrays (FPGAs) have reached capacities beyond millions of equivalent gates, it becomes possible to accelerate floating-point scientific computing applica...
Antonio Roldao Lopes, George A. Constantinides