5 search results - page 1 / 1 » Floating-Point Fused Multiply-Add: Reduced Latency for Float... |
ARITH
2005
IEEE
13 years 11 months ago
2005
IEEE
In this paper we propose an architecture for the computation of the double—precision floating—point multiply—add fused (MAF) operation A + (B × C) that permits to compute ...
ARITH
2009
IEEE
14 years 5 days ago
2009
IEEE
The paper introduces fine-grain clockgating schemes for fused multiply-add-type floating-point units (FPU). The clockgating is based on instruction type, precision and operand v...
ICPP
1999
IEEE
13 years 9 months ago
1999
IEEE
Loops are the main time consuming part of programs based on floating point computations. The performance of the loops is limited either by recurrences in the computation or by the...
TC
2010
13 years 3 months ago
2010
—Due to the widespread use and inherent complexity of floating-point addition, much effort has been devoted to its speedup via algorithmic and circuit techniques. We propose a ne...
ARITH
1999
IEEE
13 years 9 months ago
1999
IEEE
The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses "flagged prefix addition" to merge rounding with the s...