4 search results - page 1 / 1 » Floating-point sparse matrix-vector multiply for FPGAs |
ERSA
2010
13 years 3 months ago
2010
Cache-based, general purpose CPUs perform at a small fraction of their maximum floating point performance when executing memory-intensive simulations, such as those required for sp...
FCCM
2007
IEEE
13 years 6 months ago
2007
IEEE
Creating a high throughput sparse matrix vector multiplication (SpMxV) implementation depends on a balanced system design. In this paper, we introduce the innovative SpMxV Solver ...
FCCM
2006
IEEE
13 years 11 months ago
2006
IEEE
We present an architecture and an implementation of an FPGA-based sparse matrix-vector multiplier (SMVM) for use in the iterative solution of large, sparse systems of equations ar...
FPGA
2005
ACM
13 years 10 months ago
2005
ACM
Large, high density FPGAs with high local distributed memory bandwidth surpass the peak floating-point performance of high-end, general-purpose processors. Microprocessors do not...