System-on-Chip (SoC) design methodologies rely heavily on reuse of intellectual property (IP) blocks. IP reuse is a labour intensive and time consuming process as IP blocks often ...
In this paper we propose a new communication synthesis approach targeting systems with sequential communication media (SCM). Since SCMs require that the reading sequence and writi...
Jason Cong, Yiping Fan, Guoling Han, Wei Jiang, Zh...
Constraint-driven Communication Synthesis enables the automatic design of the communication architecture of a complex system from a library of pre-defined Intellectual Property (I...
Alessandro Pinto, Luca P. Carloni, Alberto L. Sang...
A simple protocol for latency-insensitive design is presented. The main features of the protocol are the efficient implementation of elastic communication channels and the automat...
Jordi Cortadella, Michael Kishinevsky, Bill Grundm...
Power consumption of system-level on-chip communications is becoming more significant in the overall system-on-chip (SoC) power as technology scales down. In this paper, we propos...
Renshen Wang, Nan-Chi Chou, Bill Salefski, Chung-K...