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2006
ACM

Synthesis of synchronous elastic architectures

10 years 27 days ago
Synthesis of synchronous elastic architectures
A simple protocol for latency-insensitive design is presented. The main features of the protocol are the efficient implementation of elastic communication channels and the automatable design methodology. With this approach, finegranularity elasticity can be introduced at the level of functional units (e.g. ALUs, memories). A formal specification of the protocol is defined and an efficient scheme for the implementation of elasticity that involves no datapath overhead is presented. The opportunities this protocol opens for microarchitectural design are discussed. Categories and Subject Descriptors: B.5.2 [Registertransfer-level implementation]: Design Aids. General Terms: Design, Theory, Verification.
Jordi Cortadella, Michael Kishinevsky, Bill Grundm
Added 13 Nov 2009
Updated 13 Nov 2009
Type Conference
Year 2006
Where DAC
Authors Jordi Cortadella, Michael Kishinevsky, Bill Grundmann
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